The present invention relates to a semiconductor device with a heterojunction bipolar transistor which uses a compound semiconductor, and to a method of manufacturing the semiconductor device.
Reduction in the emitter-base junction capacities and base-collector junction capacities of heterojunction bipolar transistors is closely associated with improvement of device performance characteristics such as an operating speed. In particular, collector-up heterojunction bipolar transistors (hereinafter, abbreviated to C-up HBTs), compared with emitter-up heterojunction bipolar transistors (hereinafter, abbreviated to E-up HBTs), have the advantages that the former can be reduced in parasitic collector capacity and enhanced in maximum oscillation frequency. However, C-up HBTs have had the problem that since an emitter-base junction area increases above a base-collector junction area, part of the electrons that have been injected from the emitter fail to reach the collector and thus that this event reduces a grounded-emitter current amplification factor (hereinafter, abbreviated to the current amplification factor). In order to prevent this problem, there is a technique for preparing an electric-current constriction structure by stacking an emitter layer, a base layer, and a collector layer, in that order, on a crystal-growing substrate and then side-etching the emitter layer. This technique is proposed by way of example in, for instance, the “Proceedings of Eighth International Conference on Indium Phosphide and Related Materials (1996), pp. 137-140”.